An estimation method for gate delay variability in nanometer CMOS technology

AUTOR(ES)
FONTE

IBICT - Instituto Brasileiro de Informação em Ciência e Tecnologia

DATA DE PUBLICAÇÃO

2010

RESUMO

In the nanoscale regime of VLSI technology, circuit performance is increasingly affected by variational effects such as process variations, power supply noise, coupling noise and temperature changes. Manufacturing variations may lead to significant discrepancies between designed and fabricated integrated circuits. Due to the shrinking of design dimensions, the relative impact of critical dimension variations tends to increase with each new technology generation, since the process tolerances do not scale in the same proportion. Many studies on how the intrinsic variability of physical processes affect the functionality and reliability of the circuits have been done in recent years. Since the process variations become a more significant problem because of the aggressive technology scaling, a shift from deterministic to statistical analysis for circuit designs may reduce the conservatism and risk that is present while applying the traditional technique. The purpose of the work is to propose a method that accounts for the deviation in the performance of transistors networks and logic gates without the need of performing computationally costly simulations. The estimation method developed uses the Elmore Delay model and the Asymptotic Waveform Evaluation (AWE), by considering the resistances of transistors obtained as functions of threshold voltages variations of the transistors in the arrangement. A pre-characterization was performed in some logic gates according to their performance variability caused by variations in the threshold voltage of the transistors by running Monte Carlo simulations. Since there are several kinds of transistor networks arrangements and they present different behavior in terms of delay, power consumption, area and variability of these metrics, it is very useful to identify circuits with such arrangements of transistors that are less influenced by variations in their parameters. The delay variability modeling relies on (2K) DC simulations for the pull-up network, (2N) DC simulations for the pull-down network (K and N are the number of transistors in the pull-up and pull-down network, respectively) and on a single transient simulation for each gate, which take only a few seconds altogether. The goal of the whole analysis is to provide guidelines for the generation of optimal logic networks that present low sensitivity to variations in their parameters.

ASSUNTO(S)

mos transistor microeletronica cmos performance variability transistor network

ACESSO AO ARTIGO

Documentos Relacionados